![]() 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity).Up to 1-GHz Sitara ARM Cortex-A8 32Bit RISC Processor.Additionally, the programmable nature of the PRU-ICSS,along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibilityin implementing fast, real-time responses, specialized data handling operations, custom peripheralinterfaces, and in offloading tasks from the other processor cores of SoC. The PRU-ICSS enables additionalperipheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS,Ethernet Powerlink, Sercos, and others. ![]() The PRU-ICSS is separate from the ARM core, allowing independentoperation and clocking for greater efficiency and flexibility. The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8processor and the PowerVRSGX Graphics Accelerator subsystem provides 3D graphics acceleration to support displayand gaming effects. The contains the subsystems shown in the Functional Block Diagram and a brief description of eachfollows: The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of eachfollows: Processor SDKLinux and TI-RTOS are available freeof charge from TI. The devices support high-level operating systems (HLOS). The AM335x microprocessors, based on the ARM Cortex-A8 processor, areenhanced with image, graphics processing, peripherals and industrial interface options such asEtherCAT and PROFIBUS.
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